Computer Organization & Architecture Winter 2022 GTU Paper Solution | 3140707

Here, We provide Computer Organization & Architecture GTU Paper Solution Winter 2022. Read the Full COA GTU paper solution given below.

Computer Organization & Architecture GTU Old Paper Winter 2022 [Marks: 70] : Click Here

(a) Draw the block diagram of 4-bit combinational circuit shifter.

Here is the block diagram of a 4-bit combinational circuit shifter:

            _________      _________      _________      _________
           |         |    |         |    |         |    |         |
[3..0] --> |  SHIFT  | -->|  SHIFT  | -->|  SHIFT  | -->|  SHIFT  | --> [3..0]
           |  LEFT   |    |   UP    |    |  RIGHT  |    |  DOWN   |
[DIR] -->  |_________|    |_________|    |_________|    |_________|

The circuit takes a 4-bit input [3..0] and a direction signal [DIR], and outputs the shifted 4-bit result. The direction signal can take four possible values: LEFT, UP, RIGHT, or DOWN, which correspond to shifting the input to the left, up (towards the most significant bit), right, or down (towards the least significant bit), respectively.

The circuit consists of four identical shift blocks, each of which shifts the input one bit in the specified direction. The output of each block is connected to the input of the next block in the sequence. The direction signal is used to control the operation of the shift blocks.

(b) Construct diagram of common bus system of four 4-bits registers with

(c) What is the role of sequence counter(SC) in control unit? Interpret its
concept with the help of its three inputs using diagram.

(a) List out names of eight main registers of basic computer with their
symbolic name and purpose.

Here are the eight main registers of a basic computer with their symbolic name and purpose:

  1. Accumulator (AC): It is used to store intermediate results of arithmetic and logical operations.
  2. Program Counter (PC): It holds the memory address of the next instruction to be executed.
  3. Memory Address Register (MAR): It holds the memory address of the data to be fetched or stored.
  4. Memory Buffer Register (MBR): It holds the data to be written to or read from memory.
  5. Instruction Register (IR): It holds the current instruction being executed.
  6. Index Register (X): It is used as a pointer to memory locations and is often used for indexing arrays.
  7. Stack Pointer (SP): It is used to keep track of the top of the stack in memory.
  8. Status Register (SR): It contains flags that indicate the outcome of the most recent arithmetic or logical operation.

(b) Summarize following addressing modes with example.
1) Implied mode 2) Register mode

(c) Which are the different phases of Instruction Cycle? Describe Register
transfer for fetch phase with its diagram.

(c) Define: microinstruction; Identify different types of 16 bits instruction
formats for basic computer using figure.

(a) Use BSA and BUN instruction with example and diagram.

BSA (Branch and Save Return Address) and BUN (Branch Unconditionally) are two types of instructions used in computer programming to change the flow of program execution.

BSA Instruction: The BSA instruction is used to call a subroutine in a program. It saves the current value of the program counter (the address of the next instruction to be executed) in a register called the Link Register and transfers control to the address specified in the instruction. The Link Register is used to return control to the instruction following the BSA instruction after the subroutine is executed.

BUN Instruction: The BUN instruction is used to transfer control to a new address unconditionally. It simply sets the program counter to the address specified in the instruction and continues execution from there.

(b) Criticize Three-Address Instructions and Zero address instruction with
common example.

(c) Describe how control unit determine instruction type after the
decoding using flowchart for instruction cycle.


(a) Prepare flowchart of CPU-IOP communication.

(b) Differentiate RISC and CISC architecture.

(c) What is cache memory? Interpret direct addressing mapping with

(a) Draw and criticize memory hierarchy in a computer system.

Memory hierarchy is an important aspect of computer architecture that aims to provide a balance between the speed and capacity of memory. The memory hierarchy consists of multiple levels of memory, each with different access times, capacities, and costs.

The different levels of memory hierarchy are:

  1. Registers: The fastest memory in a computer system, which are directly accessible by the processor.
  2. Cache: The next level of memory, which stores frequently accessed data and instructions. It is faster than main memory but has a smaller capacity.
  3. Main Memory: The main memory of the computer system, which stores the operating system, programs, and data. It is slower than cache but has a larger capacity.
  4. Secondary Storage: The long-term storage of the computer system, which includes hard disk drives, solid-state drives, and optical drives.
  5. Tertiary Storage: The archival storage of the computer system, which includes tapes and other forms of offline storage.

Criticisms of the memory hierarchy include the following:

  1. Cost: Each level of memory adds cost to the computer system, and designing a memory hierarchy that balances cost and performance can be challenging.
  2. Complexity: The memory hierarchy adds complexity to the computer system, making it more difficult to design and program.
  3. Cache coherence: Maintaining cache coherence between multiple processors can be difficult and may require additional hardware and software support.
  4. Capacity: Each level of memory has a finite capacity, which can lead to cache misses and slower performance.
  5. Latency: Accessing memory at higher levels of the hierarchy can take longer than accessing lower levels of memory, which can impact performance.

Despite these criticisms, the memory hierarchy remains an essential part of modern computer architecture, allowing for faster access to frequently used data and instructions while still providing sufficient capacity for less frequently used data and instructions.

(b) Write an Assembly level program for addition of 50 numbers.

(c) Draw the flowchart of first pass of the assembler and explain working
of the same.


(a) Interpret the following instructions: INP, ISZ and LDA

  1. INP: INP is an input instruction used in assembly language programming. It is used to input data from an input device, such as a keyboard or a scanner, into a memory location.
  2. ISZ: ISZ is an increment and skip if zero instruction. It is used to increment the contents of a memory location by 1 and then checks whether the result is zero or not. If it is zero, then the program counter is incremented by one, and the next instruction is executed. If it is not zero, the program counter is not changed, and the current instruction is repeated.
  3. LDA: LDA is a load accumulator instruction used in assembly language programming. It is used to load the contents of a memory location into the accumulator register.

(b) Write an Assembly level program to move one block of data to another

(c) List out modes of transfer. Formulate direct memory access technique
in detail.

(a) Summarize major hazards in pipelined execution.

Pipelining is a technique used in computer processors to improve performance by breaking down instructions into smaller steps that can be executed in parallel. However, pipelining can lead to hazards that can slow down the execution of instructions.

The major hazards in pipelined execution are:

  1. Structural Hazards: Occur when multiple instructions need the same hardware resource at the same time. For example, if the pipeline stages require access to the same memory or ALU, they will need to be shared. Structural hazards can be resolved by adding additional hardware or by rearranging the pipeline stages.
  2. Data Hazards: Occur when an instruction depends on the results of a previous instruction that is still being processed in the pipeline. This can cause the pipeline to stall, waiting for the results of the previous instruction. Data hazards can be resolved by forwarding the data from the previous instruction to the dependent instruction, or by stalling the pipeline until the data is available.
  3. Control Hazards: Occur when the pipeline needs to make a decision based on a conditional instruction, such as a branch instruction, before the results of the instruction are available. Control hazards can cause the pipeline to stall, waiting for the results of the conditional instruction. Control hazards can be resolved by using branch prediction techniques or by delaying the execution of conditional instructions until the results are available.

By identifying and resolving these hazards, pipelined execution can be optimized for high performance.

(b) What is a data dependency conflict in instruction pipeline?
Recommend solutions for data dependency conflicts.

(c) Demonstrate four-segment instruction pipeline in detail


(a) Sketch Microinstruction code format. Quote BR and CD field in brief.

Microinstruction code format typically includes several fields, such as the operation code (opcode), register selection fields, control fields, and address fields. One common microinstruction code format is the horizontal microinstruction format, which arranges the fields horizontally in the microinstruction word.

Here is an example of a horizontal microinstruction code format:

| opcode | RS1 | RS2 | RS3 | control fields | address field |

  • Opcode: This field specifies the operation to be performed by the microinstruction. The opcode field can be used to encode operations such as load, store, arithmetic, logic, and control operations.
  • RS1, RS2, RS3: These fields specify the registers to be used in the microinstruction. Depending on the processor architecture, these fields may specify general-purpose registers, special-purpose registers, or flags.
  • Control fields: These fields specify the control signals to be generated by the microinstruction. Examples of control fields include enable signals, clock signals, and data path signals.
  • Address field: This field specifies the memory address or the next microinstruction address to be executed.

Two common fields in the control fields are:

  • BR (Branch) field: This field specifies the type of branch to be taken by the processor. The BR field can encode different types of branches such as unconditional, conditional, and indirect branches.
  • CD (Condition) field: This field specifies the condition for a conditional branch. The CD field can encode conditions such as equal, not equal, less than, greater than, and carry. The CD field is used to compare two values and generate a control signal based on the comparison result.

(b) Compare following terms:
Write through-cache and Write back cache.
Spatial locality and Temporal locality

(c) Elaborate flynn’s classification scheme with proper diagram.

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