MPI GTU Paper Solution Winter 2022

Here are some advantages of assembly language in comparison with high-level languages:

1. Direct Control over Hardware: Assembly language provides direct access to the hardware components of the computer, such as registers and memory. This allows for fine-grained control over the computer’s operations, resulting in more efficient and optimized code.
2. Smaller Code Size: Assembly language programs are typically smaller in size than equivalent programs written in high-level languages. This is because assembly language instructions are simpler and more concise than high-level language statements, resulting in fewer instructions required to accomplish the same task.
3. Faster Execution: Assembly language programs can execute much faster than equivalent programs written in high-level languages. This is because assembly language instructions map directly to machine code, resulting in minimal overhead and faster execution.
4. Memory Efficiency: Assembly language programs can be more memory-efficient than equivalent programs written in high-level languages. This is because assembly language allows for precise control over memory allocation and usage, resulting in less wasted memory.
5. Low-Level Optimization: Assembly language provides the ability to perform low-level optimizations, such as instruction scheduling and loop unrolling, which can result in faster and more efficient code.
6. Access to System Calls: Assembly language provides direct access to system calls, allowing for more control over the operating system and its resources.

The block diagram of the Intel 8085 microprocessor consists of the following functional blocks:

1. Accumulator: The accumulator is an 8-bit register that stores the result of arithmetic and logical operations.
2. General-Purpose Registers: The 8085 has six general-purpose registers, namely B, C, D, E, H, and L. These registers can be used for storing operands, addresses, and other data.
3. Program Counter (PC): The program counter is a 16-bit register that stores the memory address of the next instruction to be executed.
4. Stack Pointer (SP): The stack pointer is a 16-bit register that points to the current top of the stack.
5. Instruction Decoder: The instruction decoder decodes the instructions fetched from memory and generates the control signals required to execute the instructions.
6. Arithmetic and Logic Unit (ALU): The ALU performs arithmetic and logical operations on the data stored in the accumulator and other registers.
7. Timing and Control Unit: The timing and control unit generates the various control signals required to execute instructions and manage the data flow between the various functional blocks.
8. Interrupt Control: The interrupt control block manages the interrupts and handles the transfer of control to the interrupt service routine.
9. Input/Output (I/O) Ports: The 8085 microprocessor has two sets of 8-bit input/output ports, namely Port A and Port B. These ports are used to interface with external devices.
10. Memory Interface: The memory interface provides the interface between the microprocessor and the memory system, allowing the microprocessor to read and write data and instructions from and to memory.

Mistake

The above program decrements the contents of register pair H-L and checks if the result is zero using the JNZ (Jump if Not Zero) instruction. If the result is not zero, the program jumps back to the label LOOP, creating an infinite loop.

Correct Program

The 8085 Programming Model is a conceptual representation of the way the 8085 microprocessor works. It consists of the following components:

1. Accumulator: A register used for arithmetic and logical operations.
2. Registers: Other registers available for general purpose use, including B, C, D, E, H, and L.
3. Program Counter (PC): A register that keeps track of the memory location of the next instruction to be executed.
4. Stack Pointer (SP): A register that keeps track of the memory location of the top of the stack.
5. Flags: A set of status flags that indicate the result of the last operation, including the Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry (CY) flags.
6. Memory: An addressable space where data and instructions are stored.

The 8085 instruction set can be classified into the following categories based on the addressing modes used:

1. Immediate addressing mode: The operand is specified directly in the instruction. Examples: MVI A, 55h, ADI 42h.
2. Register addressing mode: The operand is specified in a register. Examples: MOV A, B, ADD C.
3. Direct addressing mode: The operand is specified by a memory address. Examples: LDA 2040h, STA 3050h.
4. Indirect addressing mode: The operand is specified indirectly by a register pair that contains the memory address. Examples: LDAX B, STAX D.
5. Implicit addressing mode: The operand is implied by the instruction. Examples: NOP, HLT.

One byte instructions: These are the simplest instructions in the 8085 instruction set, and they occupy only one byte of memory. They usually perform simple operations like incrementing or decrementing a register or performing a logical operation on a register. Examples of one byte instructions are INR, DCR, CMA, etc.

Two byte instructions: These instructions occupy two bytes of memory, and they usually involve a register and an immediate data byte. The first byte specifies the operation to be performed, while the second byte provides the operand data. Examples of two byte instructions are MVI, LXI, STA, etc.

Three byte instructions: These instructions occupy three bytes of memory, and they are used for more complex operations like transferring data between memory locations or performing arithmetic operations on large data values. Examples of three byte instructions are MOV, ADD, SUB, etc.

There are three different types of instruction sets in 8085 microprocessor:

• Data transfer group: This group of instructions is used to transfer data between registers, memory locations, and input/output ports. Examples of instructions in this group are MOV, MVI, LDA, STA, etc.

• Arithmetic group: This group of instructions is used to perform arithmetic and logical operations on data. Examples of instructions in this group are ADD, SUB, INR, DCR, CMA, etc.

• Control transfer group: This group of instructions is used to change the sequence of execution of instructions based on certain conditions. Examples of instructions in this group are JMP, JC, JZ, CALL, RET, etc.

Maskable Interrupts: Maskable interrupts are those that can be disabled or enabled by software. It means that the microprocessor can be programmed to ignore a maskable interrupt. The maskable interrupts are used for low-priority interrupt requests that can be delayed or ignored without affecting the system’s operation. Examples of maskable interrupts are external interrupts, keyboard interrupts, and serial communication interrupts.

Non-Maskable Interrupts: Non-Maskable Interrupts (NMIs) are the interrupts that cannot be disabled or ignored by the microprocessor. These interrupts are designed for critical events such as power failure, memory parity errors, or system reset. The microprocessor must respond to NMIs immediately to prevent the system from crashing or losing data. The NMIs have the highest priority and can interrupt the microprocessor at any time.

In the 8085 microprocessor, the flag register is an 8-bit register that contains 5 flags that are set or reset based on the result of the arithmetic and logical operations performed by the processor. The 5 flags are:

Sign (S) flag: It indicates whether the result of an operation is positive or negative. If the MSB of the result is 1, the flag is set, indicating a negative result. If the MSB is 0, the flag is reset, indicating a positive result.

Zero (Z) flag: It indicates whether the result of an operation is zero or not. If the result is zero, the flag is set, else it is reset.

Auxiliary Carry (AC) flag: It indicates whether a carry occurred from bit 3 to bit 4 during an arithmetic operation involving lower nibbles. If a carry occurred, the flag is set, else it is reset.

Parity (P) flag: It indicates whether the result of an operation has an even or odd number of 1s in its binary representation. If the result has an even number of 1s, the flag is set, else it is reset.

Carry (CY) flag: It indicates whether a carry occurred from the most significant bit during an arithmetic operation. If a carry occurred, the flag is set, else it is reset.

Vectored Interraupts

A vectored interrupt is an interrupt that has a predefined vector address associated with it. When the interrupt occurs, the microprocessor or microcontroller automatically jumps to the vector address to execute the corresponding interrupt service routine (ISR).

In other words, the interrupt vector specifies the memory location of the ISR. Vectored interrupts are faster and more efficient as the microprocessor or microcontroller does not have to search for the ISR address.

Non-Vectored Interraupts

A non-vectored interrupt does not have a predefined vector address associated with it. When the interrupt occurs, the microprocessor or microcontroller must search for the ISR address using a software routine.

Non-vectored interrupts are slower and less efficient than vectored interrupts, as they require additional processing time to find the ISR address.

(1) READY PIN:

• The READY pin is used to synchronize the operation of the microprocessor with slower external devices such as memories and input/output (I/O) devices.
• When the READY pin is high, it indicates that the external device is ready to accept or provide data to the microprocessor. The microprocessor will only execute an instruction when the READY pin is high. If the READY pin is low, the microprocessor will wait until it goes high before executing the next instruction.

(2) ALE (Address Latch Enable):

• The ALE signal is used to latch the address from the microprocessor onto the address bus. The address is latched by external devices such as memories and I/O devices, so they know which device the microprocessor is communicating with.

(3) HOLD:

• The HOLD pin is used by external devices to request control of the address and data buses. When a device sends a HOLD request, the microprocessor completes the current instruction and sends out a HOLD ACK (acknowledge) signal.
• The external device can then take control of the address and data buses and perform its operation. Once the operation is complete, the external device sends a HOLD RELEASE signal to relinquish control back to the microprocessor.

(4) X1 and X2:

• These are the crystal oscillator pins used to provide the clock signal to the microprocessor. A crystal oscillator circuit is connected to these pins to generate the clock signal. The clock signal is used to synchronize the operation of the microprocessor and other devices.

(5) SID and SOD:

• SID (Serial Input Data) and SOD (Serial Output Data) pins are used for serial communication. The microprocessor can communicate with external devices using serial communication protocols. The SID pin is used to input serial data to the microprocessor, while the SOD pin is used to output serial data from the microprocessor.

(6) IO/M:

• The IO/M (Input/Output or Memory) pin indicates whether the microprocessor is performing an I/O or memory operation. When the IO/M pin is low, the microprocessor is performing a memory operation. When the IO/M pin is high, the microprocessor is performing an I/O operation.

(7) HLDA (Hold Acknowledge):

• The HLDA signal is used to acknowledge a HOLD request from an external device. When a device sends a HOLD request, the microprocessor completes the current instruction and sends out a HOLD ACK signal.
• The external device can then take control of the address and data buses and perform its operation. Once the operation is complete, the external device sends a HOLD RELEASE signal to relinquish control back to the microprocessor.

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Interrupt Inputs: The 8259 chip has eight interrupt inputs (INT0 to INT7) that can be connected to various sources in the computer system. Each of these inputs can be enabled or disabled using control registers.

Interrupt Request Register (IRR): The IRR is an 8-bit register that stores the interrupt requests from the interrupt inputs. Each bit in the register corresponds to an interrupt input.

Interrupt In-Service Register (ISR): The ISR is an 8-bit register that stores the interrupts that are currently being serviced by the microprocessor. Each bit in the register corresponds to an interrupt input.

Interrupt Mask Register (IMR): The IMR is an 8-bit register that is used to enable or disable interrupts from the interrupt inputs. Each bit in the register corresponds to an interrupt input.

Priority Resolver: The priority resolver is a logic circuit that determines the highest priority interrupt request that needs to be serviced by the microprocessor. It selects the interrupt with the highest priority and sends its interrupt number to the microprocessor.

Control Logic: The control logic includes various control registers and control signals that are used to manage the interrupts. It includes the Initialization Command Word (ICW) register, the Interrupt Mask Command (IMC) register, and the End of Interrupt (EOI) signal.

Cascade Buffer: The 8259 chip can be cascaded with other 8259 chips to handle more than eight interrupts. The cascade buffer is a set of pins that allow multiple 8259 chips to be connected together.

Control Logic: The control logic includes various control registers and control signals that are used to configure and manage the operation of the chip. It includes the Control Word Register (CWR), the Mode Set Register (MSR), and various control signals such as RD, WR, and CS.

Data Bus Buffer: The data bus buffer is used to buffer the data between the chip and the CPU.

Port A: Port A is an 8-bit bidirectional I/O port that can be configured as input or output.

Port B: Port B is an 8-bit bidirectional I/O port that can be configured as input or output. It also includes two control signals, STB (Strobe) and CLK (Clock), that are used for handshake operations.

Port C: Port C is an 8-bit port that can be divided into two parts, Port C Lower (PC0-PC3) and Port C Upper (PC₄-PC₇). The Lower part can be configured as input or output, while the Upper part can be used for various modes of operation such as mode 0, mode 1, and mode 2.

Mode Set Register: The Mode Set Register (MSR) is used to configure the operation of the chip. It includes various control bits that are used to select the mode of operation for each port.

Control Word Register: The Control Word Register (CWR) is used to configure the operation of the chip. It includes various control bits that are used to select the mode of operation for each port, and to enable or disable the various features of the chip.